FPGA design and implementation for adaptive digital chaotic key generator

Abstract

Background

Information security is very important in today’s digital world, especially cybersecurity. The most common requirement in securing data in all services: confidentiality, digital signature, authentication, and data integrity is generating random keys. These random keys should be tested for randomness. Hardware security is more recommended than software. Hardware security has more speed and less exposure to many attacks than software security. Software security is vulnerable to attacks like buffer overflow attacks, side-channel attacks, and Meltdown–Spectre attacks.

Results

In this paper, we propose an FPGA Implementation for the adaptive digital chaotic generator. This algorithm is proposed and tested before. We introduce its implementation as hardware. This algorithm needs a random number seed as input. We propose two designs. The first one has an input random number. The second one has PRNG inside. The target FPGA is Xilinx Spartan 6 xc6slx9-2-cpg196. We used MATLAB HDL Coder for the design. We propose a configurable Key block’s length. For 32 bit the maximum frequency is 15.711 MHz versus 11.635 MHz for the first and second designs respectively. The area utilization of the Number of Slice Registers is 1% versus 2%. The number of Slice Look Up Tables is 40% versus 59%. number of bonded input output blocks is 64% versus 66%. otherwise are the same for the two designs.

Conclusions

In this paper, we propose an efficient and configurable FPGA Design for adaptive digital chaotic key generator. Our design has another advantage of storing the output keys internally and reading them later.

Background

Nowadays, generating a cryptographic random number generator is very important. Its importance comes from information security importance, cyber security, and testing machine learning. How to generate pseudo-random numbers is a question to which we’ll pick an answer of it and introduce a hardware Implementation to it over the FPGA. The FPGA Design is performed by MATLAB HDL Coder (MathWorks 2023). Its workflow is shown in Fig. 1. In Fig. 1 there are two input methods either by Simulink or Matlab script. Our work is based on a Matlab script. MATLAB HDL Coder needs two files; the first one is the top level of the design and the other is its test. After creating the HDL CODER project, we select only, the top function of the design and its tester. Then the HDL CODER converts this script to an HDL file. The HDL file is then forwarded to the FPGA’s vendor synthesizer. The generation of the HDL code from the MATLAB script requires understanding the I/O types. This is necessary for the FPGA pins. It also requires making all types compatible with each other. It also requires identifying all the used functions and libraries such that all functions could be mapped into hardware. Functions like printf and scanf are examples of not supported functions. The MATLAB HDL Coder as a tool for FPGA Design was a subject for evaluation by many researchers. They first recommended using it for only fast proofing of the idea. This was the result of area utilization and speed compared to the VHDL is not encouraging (Elsayed and Kayed 2022). However, the latest research has proposed an Optimization technique to dramatically, improve the result (Kayed and Elsayed 2022). Based on that recommendation we here design and implement the key generation over the FPGA using MATLAB HDL Coder. We selected the new chaotic random numbers key generator (Soleit 2018) which was published by Elsayed A. Soleit T 2018. Soleit is one of the authors of this paper so, we already have a tested Algorithm that can generate a cryptographic random number generator written and tested as a MATLAB script. Figure 2 shows the Block Diagram of the new adaptive chaotic key generator (Soleit 2018). this was already, written by MATLAB script in previous research, and fortunately, the author of this research is one of the authors of this paper, Fig. 3 illustrates the given simulation code. Therefore, the code is one of the givens of this research. We can notice that the input depends on the rand (x) function which is built in MATLAB. All the scripts can be hardware implemented except this function. In Fig. 2 we can see the adaptive coefficients from c1 to cN, here we selected N to be three to just prove the idea. However, the design is configurable and we can easily change Nc, where Nc is the number of the coefficients $-$ 1. This block diagram is the representation of the following equations:

$$\begin{aligned} y_k= & {} Z_k+\sum _{i=0}^{N}C_iy_{k-i} \end{aligned}$$

(1)

$$\begin{aligned} \mod (y)= & {} y-2\times \lfloor \frac{y+1}{2} \rfloor \end{aligned}$$

(2)

$$y_{k} = \bmod \left( {Z_{k} + \sum\limits_{{i = 0}}^{N} {C_{i} } y_{{k - i}} } \right),\;y_{i} \in I = \left( { - 1,1} \right)$$

(3)

where Zk is the seed, in the simulation code illustrated in Fig. 3, it is stored in variable x and initialized by rand (). Again, the Rand function can’t be implemented over the FPGA. Rand itself should be replaced with a method that generates its output. To generate a random seed we adopted a published algorithm in (Soleit 2018). The Hardware Implementation of this part is subject to another publication. This algorithm depends on the accuracy of calculating the square root and gives some sort of randomness in the fractional part. The first order is represented by Eq. (4) and the second order is represented by Eq. (5). This algorithm was also already both simulated and tested.

$$x_{{i + 1}} = \sqrt ( x_{i} )\bmod 1 \times 10^{n}$$

(4)

$$x_{{i + 1}} = \sqrt {\left( {x_{i} + x_{{i - 1}} } \right)} \bmod 1 \times 10^{n}$$

(5)

We here used the second order (Su and McSweeney 2019) to supply our main algorithm with the required random input. In the following section, we will illustrate the design process from the starting point of the simulated algorithm by Matlab script to the implementation of the FPGA.

Fig. 1

MATLAB HDL Coder Workflow (Eda techchannel OpenSystems Media 2023)

Fig. 2

New adaptive chaotic key generator block diagram

Fig. 3

Original MATLAB Code

Fig. 4

Cahaos1 function’s code after modification

Fig. 5

Cahaos Top view

Fig. 6

MATLAB script for Cahaos function

Fig. 7

Cahaos Tester Code

Fig. 8

The plot of the output of the Adaptive chaotic random number generator

Fig. 9

Top level of the chaotic random number key grnerstor based on swuare root PRNG seed

Fig. 10

Script of cahaos_sqrt_rand_top

Fig. 11

Code for the tester of Top view of cahaos_sqrt_rand_top

Methods

Chaotic Random Number generator Design is done using MATLAB HDL Coder. The Block Diagram of Fig. 2 was written by MATLAB just for simulation and testing. As we mentioned its code is introduced in Fig. 3, some modifications should be done to the code the make it suitable to be valid for the generation of the HDL code. Figure 4 illustrates the modified code. We used the fixed-point numeric object to unify almost all the types. Values of nbits and n fractions are word length and fraction length respectively. The memory size is configurable by the variable nsamp. We here put the Nc variable equal to 2 in the code and this implies three coefficients c1, c2, and c3. This is the main function that takes the input random number and the feedback ’s’ for sum and ’C’ for coefficients. The outputs are the random number, also used for feedback, and the two feedback feed the inputs with sum and c. This function itself needs to be embedded into another function to connect the feedback with the inputs, this function is called Cahaos. Figure 5 shows the top view of the Cahaos design. The Figure illustrates the inputs and the outputs. We have a 32-bit input random number as a seed and we have output to the generated chaotic random number. The output is also 32-bit. We have also a clock and clock enable input pins, CLK and clk_enable respectively. We have also input reset and output enable ce_out. As recommended by Kayed and Elsayed (2022) we used the persistent keyword to generate registers on the feedback signal. This improves both the area and speed. In Fig. 6 the code of this function is illustrated. After defining the persistence for the three feedback, we just call the cahaos1 function and then connect the inputs with the outputs The second file needed by the MATLAB workflow is the tester. Figure 7 illustrates the code for the tester. Here we call the cahaos function 512 times. As we can see all variables are configurable and we can easily change them. The tester output is illustrated in Fig. 8. For that, the design is implemented. Frequency and its area utilization are discussed in section five. Now we will introduce the design by adding a module that generates a random seed. The new design is called cahaos_sqrt_rand_top. So instead of feeding the design input with a random number we just feed it with a non-square number. This non-square number is go through equ 5 to generate the required random seed. The design of this part is out of the scope of this paper. We also supported the design with a memory to store the generated output and we can read this memory by activating the input read signal Rd. In Fig. 9 the top view of cahaos_sqrt_rand_top is illustrated. We here output the valid output that indicates the finishing of the square part. Also, the LOAD/CALC input is used for loading the input non-square number and then starting to calculate the square root. These were the inputs and the outputs different from the previous design. The code and its testing are illustrated in Figs. 10 and 11 respectively.

Results

The Target Device is Xilinx Spartan 3 xc6slx9-2-cpg196 FPGA (Digilent 2023). The estimated values for device utilization for design 1 and design 2 are illustrated in Tables 1 and 2 respectively. For 32 bit the maximum frequency is 15.711 MHz versus 11.635 MHz for the first and second designs respectively. The area utilization of the Number of Slice Registers is 1% versus 2%. The number of Slice LUTs is 40% versus 59%. The number of fully used LUT-FF pairs is 5% versus 8%. The number of bonded IOBs is 64% versus 66%. The number of BUFG/BUFGCTRL/BUFHCEs and the Number of DSP48A1s are the same for the two designs 6% and 100%. In this paper, we propose an efficient and configurable FPGA Design for adaptive digital chaotic key generator. Our design has another advantage of storing the output keys internally and reading them later.

Table 1 The estimated values for device utilization for Design1

Table 2 The estimated values for device utilization for design 2

Discussion

The usage of the Chaotic is very wide. In Kumar et al. (2023) A combined chaotic key generator (CCKG) is proposed to enhance key sensitivity and generation to improve the security of medical images to be encrypted. In Kiran and Parameshachari (2022) they combine the image encryption and chaotic system to improve the security. In Sha et al. (2023) the paper proposed an image encryption algorithm using a hybrid of three modified and improved chaotic one-dimensional (1D) maps to avoid the shortcomings of 1D maps and multidimensional (MD) maps. In Zhao et al. (2023) they enhanced the randomness of the constructed chaotic system and expand its key space. In Yildirim and Tanyildizi (2023) The Mode2(x) method and the unpredictable nature of chaotic systems are used for random number generation. In Bonny et al. (2023) The paper presented a new, highly secure chaos-based secure communication system that combines a conventional cryptography algorithm with two levels of chaotic masking technique. In Al-Saadi and Alshawi (2023) they introduce Light Encryption Device (LED) which is a high-performance, lightweight block encryption solution that works on resource-constrained devices and considers a lighter version of AES. They provided Chaos-based encryption as an exceptionally high level of security because of the unique characteristics of chaotic systems. In Bonilla et al. (2016) they introduced a true random number generator based on chaos.

Many PRNGs are implemented as an example of FPGA implementation of PRNG (Rezk et al. 2019). They also adopted an already published and tested algorithm and implemented it on the FPGA (XC5VLX50T), a large FPGA compared to ours. Their implementation has utilized 1.4% and 16.7% of the available slices and DSP blocks respectively. this is huge utilization compared to ours The Maximum frequency was 78which which is much faster than ours. They didn’t use MATLAB HDL Coder. The most usage of the PRNG is for key generation, key generation over FPGA can be found in Srinivas and Janaki (2021) and Naiem et al. (2009). Many other implementations of chaotic over FPGA for many applications like Abd El-Maksoud et al. (2020), Tutueva et al. (2020), Al-Musawi et al. (2021) and Dridi et al. (2020).

Conclusions

In this paper, we introduced the design and implementation of an adaptive chaotic key generator over FPGA. The design and its implementation were done by using MATLAB HDL Coder. The target FPGA was Xilinx Spartan 3 xc6slx9-2-cpg196. We introduced two designs; design 1 was the implementation of the algorithm with a random seed input. and design 2 was the implementation of the algorithm with input non-square number and the random seed is internally generated. Design 2 also has memory to store the generated output that can be accessed later. For design 1, the area utilization was for design 1, 189 slice registers, 2303 slice LUTs (lookup tables), 126 fully used LUT, 68 IOs, and 16 DSP blocks. is the maximum frequency was 15.711 MHz. While for design 2, the area utilization was 304 slice registers, 3380 slice LUTs (lookup tables), 276 fully used LUT, 70 IOs, and 16 DSP blocks. is the maximum frequency is 11.635 MHz.