Table 2 The estimated values for device utilization for design 2
From: FPGA design and implementation for adaptive digital chaotic key generator
Logic utilization | Used | Available | Utilization (%) |
|---|---|---|---|
Number of Slice Registers | 304 | 11440 | 2 |
Number of Slice LUTs | 3380 | 5720 | 59 |
Number of fully used LUT-FF pairs | 276 | 3408 | 8 |
Number of bonded IOBs | 70 | 106 | 66 |
Number of BUFG/BUFGCTRL/BUFHCEs | 1 | 16 | 6 |
Number of DSP48A1s | 16 | 16 | 100 |