Table 1 The estimated values for device utilization for Design1
From: FPGA design and implementation for adaptive digital chaotic key generator
Logic utilization | Used | Available | Utilization (%) |
|---|---|---|---|
Number of Slice Registers | 189 | 11440 | 1 |
Number of Slice LUTs | 2303 | 5720 | 40 |
Number of fully used LUT-FF pairs | 126 | 2366 | 5 |
Number of bonded IOBs | 68 | 106 | 64 |
Number of BUFG/BUFGCTRL/BUFHCEs | 1 | 16 | 6 |
Number of DSP48A1s | 16 | 16 | 100 |